The present invention relates to a semiconductor device, semiconductor integrated circuit such as an insulating gate field-effect transistor and a manufacturing method thereof.
Particularly, the present invention relates to an active-matrix electro-optical device and, more particularly, to a field-effect transistor which can be applied to an active-matrix liquid-crystal electro-optical device or the like and has definite switching characteristics. Also, the invention relates to a method of fabricating such a field-effect transistor.
The prior art thin-film insulated-gate field-effect transistor used in an active-matrix liquid-crystal electro-optical device is constructed as shown in FIG. 2. A blocking layer 208 is formed on an insulating substrate 209. A semiconductor layer having a source 204, a drain 205, and a channel region 203 is formed on the blocking layer 208. A gate-insulating film 202 and a gate electrode 201 are laminated on the semiconductor layer. An interlayer insulating film 211 is formed on the gate-insulating film 202 and on the gate electrode 201. A source electrode 206 and a drain electrode 207 are formed on the interlayer insulating film 211 and on the semiconductor layer.
This prior art insulated-gate FET is manufactured in the sequence described now. First, the blocking layer 208 is formed on the glass substrate 209 by sputtering while using SiO2 as a target. Then, the semiconductor layer is formed by plasma-assisted CVD and patterned to form the semiconductor layer which will have the source, drain, and channel region. Then, silicon oxide is sputtered to form the gate-insulating film 202. Subsequently, an electrically conductive layer which is heavily doped with phosphorus and used to form the gate electrode is formed by low-pressure CVD. The conductive layer is then patterned to form the gate electrode 201. Thereafter, dopant ions are implanted while using the gate electrode as a mask, so that the source 205 and the drain 204 are fabricated. Then, the laminate is thermally treated to activate it.
In the insulated-gate FET fabricated in this way, the length of the gate electrode 201 taken in the longitudinal direction of the channel is substantially identical with the channel length, indicated by 210. In the case of the n-channel structure, the current-voltage characteristic of the FET of this structure is shown in FIG. 3. This FET has the disadvantage that in the reverse bias region 250, the leakage current increases with increasing the voltage applied between the source and drain. Where this device is used in an active-matrix liquid-crystal electro-optical device, if the leakage current increases in this way, the electric charge stored in a liquid crystal 302 by a writing current 300 is discharged as a leakage current 301 through the leaking portion of the device during the non-writing period, as shown in FIG. 5(A). In this manner, it has been impossible to obtain good contrast.
A conventional method of solving this problem is to add a capacitor 303 for holding electric charge, as shown in FIG. 5(B). However, in order to form such capacitors, capacitive electrodes made of metal interconnects are needed. This results in a decrease in the aperture ratio. Also, it is reported that the aperture ratio is improved by fabricating the capacitors from transparent electrodes of ITO. Nonetheless, this scheme necessitates an excess process and hence has not enjoyed popularity.
Where only one of the source and drain of this insulated-gate FET is connected with a capacitive device or a capacitor and this transistor is used as a switching device, e.g., in the case of a well-known dynamic random access memory (DRAM) of the 1 transistor/cell type or in the case of an active liquid crystal display having pixels each of which has the circuit shown in FIG. 5(A) or 5(B), it is known that the voltage at the capacitor device is varied by the existence of a parasitic capacitance between the gate electrode and the drain or source.
The variation xcex94V in this voltage is in proportion to the gate voltage VG and to the parasitic capacitance and is in inverse proportion to the sum of the capacitance of the capacitive device and the parasitic capacitance. Therefore, it is customary to fabricate the transistor by the self-aligning technology to reduce the parasitic capacitance, thus suppressing variations in the voltage. However, as the dimensions of devices decrease, the contribution of the parasitic capacitance becomes so large that it can no longer be neglected even if the self-aligning process is exploited.
In an attempt to reduce the variation xcex94V, a new method has been proposed. In particular, as shown in FIG. 5(B), a capacitor other than the proper capacitive device is connected in parallel to increase the apparent capacitance of the capacitive device. As described previously, however, the increase in the area of the capacitor cannot be neglected for DRAMs. The decrease in the numerical aperture cannot be neglected for liquid-crystal displays.
Conventionally, a conductive material in single-layers or multilayers was utilized as a wiring material or an electrode material of a semiconductor device(semiconductor element) of an insulating gate field-effect transistor and a semiconductor integrated circuit utilizing a number of them. By overlaying such wirings with insulating films between them, it was comparatively easy to form the wirings.
In the conventional method, it was a problem that short circuit between an upper wiring and a lower wiring happened many times because insulation between wirings was made by an insulating film of 1 xcexcm thickness at most (In many cases, it was a single-layer.). This short circuit was mainly caused by bubbles, holes(pin holes), dusts and the like made in the insulating film. Conventionally, in a semiconductor integrated circuit formed especially on a silicon single-crystal substrate, an insulating film was formed of a material like phosphosilicate glass, and was half melted at a high-temperature of approximately 1000xc2x0 C. Thus insulating property between wirings was improved by making the bubbles or pin holes disappeared. This process can also make smoother the unevenness generated on the substrate by each process of forming a thin film. It was prominently effective especially to prevent disconnection of metal wires formed on the insulating film.
However, this method is not applicable to every kind of semiconductor devices and integrated circuits. It is quite natural that this method is not applicable to semiconductor devices and integrated circuits utilizing a material which is not proof against such a high temperature. For example, this method is not applicable to a cheap glass substrate of which distortion point is usually 750xc2x0 C. or less. A material like aluminum to decrease resistance as a wiring could not be utilized, either.
Generally, a higher process temperature needed better heat resistance for the device in the process. This made equipment investment huge. The bigger an object like a substrate to be treated became, the more the amount of investment became exponentially. For example, when a thin film transistor(TFT) is produced to use it as a big liquid crystal display, the size of the substrate should be 300 mmxc3x97300 mm or bigger, and it was actually impossible to adopt a high temperature process as high as 1000xc2x0 C.
The present invention was made to solve above problems, and is aimed at obtaining bigger effects by a totally creative method which has never been thought of before.
It is an object of the present invention to provide an insulated-gate FET free of the foregoing problems.
The above object is achieved by an insulated-gate FET in which the channel length, i.e., the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel (the direction of the channel length), whereby offset regions are formed in those portions of the channel regions which are in contact with the source and drain regions, respectively. The offset regions undergo no or very weak electric field from the gate electrode. The current-voltage characteristic of this device is shown in FIG. 4.
It is another object of the invention to provide a method for forming the insulated-gate FET described in the preceding paragraph.
Other objects and features of the invention will appear in the course of the description thereof which follows.
Referring to FIG. 1, the fundamental structure of a field-effect transistor according to the invention is shown. This transistor has an insulating substrate 105 and a blocking layer 104 formed on the substrate 105. A semiconductor layer which becomes a source region 100, a drain region 101, and a channel region 109 is formed on the blocking layer 104. A gate-insulating film 110 is formed on the channel region 109. A gate electrode 111 is formed on the gate-insulating film 110. An oxide layer 112 which is an insulating layer is formed on the gate electrode 111. The oxide layer 112 is formed by anodizing a material which can be anodized. A source electrode 102 and a drain electrode 103 are formed so as to be in contact with the source region and the drain region, respectively. No interlayer insulator is shown in FIG. 1, but where the parasitic capacitance between the gate electrode or the interconnects to this gate and the source, the drain, or the interconnects to the source or drain poses a problem, an interlayer insulator may be formed in the same way as in the prior art techniques. Examples of this will be described later.
Referring still to FIG. 1, the gate electrode portion which becomes the gate electrode 111 and the oxide layer 112 is made of a material that can be anodized. The surface portion of the gate electrode portion is anodized to form the oxide layer 112. The distance between the source region 100 and the drain region 101 which are to be implanted with ions, i.e., the channel length 108, is larger than the substantial length of the gate electrode 111 taken in the longitudinal direction of the channel by a length which is about twice as large as the thickness of the oxide layer 112. The gate electrode portion comprises metal or semiconductor. Chiefly, the material of the gate electrode portion is one selected from titanium (Ti), aluminum (Al), tantalum (Ta), chromium (Cr), and silicon (Si). Alternatively, the gate electrode portion is made of an alloy of some of these materials.
As a result, those portions 106 and 107 of the channel region 109 which are on the opposite sides of the gate-insulating film 110 from the portions of the oxide layer 112 formed on both sides of the gate electrode receive no electric field from the gate electrode or experience much weaker field than the portions immediately under the gate electrode. These regions 106 and 107 are hereinafter, especially where they are comparable to the channel region in crystallinity and dose, referred to as the offset regions.
These regions 106 and 107 can be made of doped amorphous materials. More strictly, it is only necessary that the regions 106 and 107 be inferior in crystallinity to the adjacent source region 100 and drain region 101. For example, if the source region 100 and the drain region 101 consist of polysilicon having large crystal grains, then it is only necessary that the regions 106 and 107 be made of amorphous silicon or semi-amorphous silicon that is slightly superior in crystallinity to amorphous silicon. If the regions 100 and 101 are made of semi-amorphous silicon, the regions 106 and 107 can be made of amorphous silicon. Of course, these amorphous materials are required to be sufficiently treated so that they behave as semiconductors. As an example, in order to minimize dangling bonds, it is necessary that these bonds be sufficiently terminated by hydrogen or a halogen element.
A good TFT (thin-film transistor) characteristic as shown in FIG. 9(a) could be obtained by forming these amorphous regions. FIG. 9(b) shows the current-voltage characteristic of a thin-film transistor of the prior art insulated-gate transistor structure. As can be seen by comparing these characteristic curves, very large leakage current was observed in the reverse direction when the prior art method was used. In accordance with the present invention, substantially amorphous regions are formed, thus improving the characteristic. That is, formation of doped amorphous regions yields the same advantages as the formation of the previously described offset regions.
Why the formation of the amorphous regions improves the characteristic is not fully understood. One possible cause is as follows. In the amorphous regions, the added dopant element is ionized at a lower rate than in the crystal regions. Therefore, if dopants are added at the same dose, the amorphous regions behave as though they had lower dopant concentrations. That is, regions substantially similar to lightly doped drains are formed. For instance, the ionization rate of silicon in amorphous state is 0.1-10% at room temperature, which is much lower than the ionization rate of almost 100% of single-crystal or polycrystal semiconductors.
Another possible cause is that the bandgap in amorphous state is larger than the bandgap in crystalline state. For example, this can be explained away by the energy band diagrams of FIGS. 9, (e) and (f). In transistors of normal, lightly doped drain structure, the energy bands between the source, channel, and drain are shown in FIGS. 9, (c) and (d). The central raised portion indicates the channel region. The staircase portions indicate lightly doped drain regions. FIG. 9(c) indicates the case in which no voltage is applied to the gate electrode. When a large negative voltage is applied to the gate electrode, the condition shown in FIG. 9(d) appears. At this time, forbidden bands exist between the source and the channel region and between the channel region and the drain to thereby inhibit movement of carries such as electrons and holes. However, the carriers pass across the gap by the tunnel effect or by hopping the trap level within the bandgap. In normal thin-film transistors (TFTs) which are not of the lightly doped drain structure, the gap width is smaller and so electric current flows more easily. This is considered to be the leakage in the reverse direction. This phenomenon is especially conspicuous for TFTs and possibly caused by numerous trap levels due to grain boundaries because TFTs are made of inhomogeneous materials such as polycrystals.
Where the bandgap in the lightly doped drain region is increased, the above-described leakage in the reverse direction decreases. This example is shown in FIGS. 9, (e) and (f). FIG. 9(e) shows the condition in which no voltage is applied to the gate. FIG. 9(f) shows the condition in which a large negative voltage is applied to the gate. When a negative voltage is applied as shown in FIG. 9(f), the width of the gap between the source and channel region and the width of the gap between the channel region and the drain are larger than those in case of FIG. 9(d), as can be seen by comparing FIG. 9(f) with FIG. 9(d). The tunnel effect is affected greatly by the width of the tunnel barrier (in this case the width of the gap). The probability that carriers tunnel through the gap is reduced greatly with increasing the width of the gap slightly. Also, hopping via local energy levels is a composite tunnel effect and, therefore, if the width of the gap increases, the probability drops drastically. For these reasons, formation of lightly doped drain regions having large bandgaps is considered as advantageous. The bandgaps of amorphous silicon is 1.5 to 1.8 eV, while the bandgap of polycrystalline silicon is 1.1 eV. If materials having such wide bandgaps are used in lightly doped drains, a quite ideal situation occurs.
To fabricate a semiconductor device in accordance with the present invention, especially a semiconductor device having the aforementioned offset regions, the gate electrode portion is formed out of a material capable of being anodized after the semiconductor layer becoming the source, drain, and the channel region and the gate-insulating layer 110 are formed. Subsequently, dopant ions which impart p- or n-type to the semiconductor layer are implanted into this semiconductor layer to form the source region 100 and the drain region 101. Thereafter, the surface of the gate electrode portion is anodized (anodic oxidized) to form the gate electrode 111 and the oxide layer 112. Thereafter, a thermal treatment or other step is carried out.
Alternatively, after forming the semiconductor layer and the gate-insulating layer 110, the gate electrode portion is fabricated out of a material that can be anodized, followed by anodization (anodic oxidation) of the surface of the gate electrode portion to form the gate electrode 111 and the oxide layer 112. Then, dopant ions are implanted into the semiconductor layer to impart p- or n-type to it, forming the source region 100 and the drain region 101. Thereafter, a thermal treatment is effected.
By carrying out these steps, insulated-gate FETs in which the channel length is greater than the length of the gate electrode taken in the longitudinal direction of the channel can be easily and certainly fabricated without producing variations in the performance which would otherwise be caused by mask misalignment.
Another method of fabricating the novel semiconductor device having amorphous regions is initiated by forming the semiconductor layer becoming the source, drain, and channel region and the gate-insulating layer 110. Then, the gate electrode portion is fabricated from a material that can be anodized. Subsequently, dopant ions are implanted so that the semiconductor layer is doped p- or n-type. As a result, the semiconductor layer is made amorphous. The source region 100, the drain region 101, and their adjacent amorphous regions 106 and 107 are formed. Thereafter, the surface portion of the gate electrode portion is anodized to form the gate electrode 111 and the oxide layer 112. At this time, the surface of the gate electrode is made to retreat by the oxidation. Then, only the source region 100 and the drain region 101 may be recrystallized while using the gate electrode portion as a mask by a self-aligning process employing laser annealing or flash lamp annealing techniques. This process is of the self-aligning type, because the gate electrode portion shades the underlying doped regions located under the gate electrode portion, thus inhibiting recrystallization of these doped regions.
Where an ion implantation process is utilized, the spreading of the doped regions due to secondary diffusion of ions can be calculated from the acceleration energy of the ions. Also, the retreat of the gate electrode is determined by the thickness of the oxide layer and so the retreat is also taken as a design parameter. In accordance with the present invention, the positional relation between the gate electrode and the doped regions can be optimized by accurate design. In particular, the thickness of the oxide layer can be controlled to tolerances less than 10 nm. Also, the secondary scattering produced during ion implantation can be controlled to tolerances of the same order. Consequently, the positional relation can be controlled to tolerances less than 10 nm during the fabrication.
In this way, the invention requires no further accurate mask alignment. The possibility that the production yield is deteriorated by the invention is low. Rather, the inventive device has greatly improved characteristics.
The present invention is aimed at providing an insulating film formed around at least one wiring and formed of the material for the wiring. It is desirable to form such an insulating film by oxidizing the material so as not to make bubbles or pin holes. Anodic oxidation, plasma oxidation method, or thermal oxidation method is desirable as a method of oxidation. As an appropriate material of the wiring, simple substances, semiconductors, or alloys of silicon, aluminum, tantalum, titanium, tungsten, or molybdenum, and what is more, a metal compound in a condition of not being oxidized, such as tantalum nitride, titanium nitride, tungsten silicide, and molybdenum silicide is appropriate. For example, a nitride like tantalum nitride changes to be tantalum oxide by anodic oxidation.
A semiconductor device in accordance with the present invention comprises:
a substrate;
a gate electrode of a transistor provided on said substrate;
a first wiring provided on said substrate in the same layer as said gate electrode; and
a second wiring provided in a layer different from said same layer,
wherein said first wiring and said second wiring cross each other, and said first wiring is provided with an oxide of a material of said first wiring on an upper or side surface of said first wiring, and said gate electrode is provided with an oxide of a material of said gate electrode on an upper or side surface of said gate electrode at a thickness different from that of said oxide of the material of said first wiring at the crossing.
The semiconductor device further comprises source and drain regions on the substrate, a channel region provided on the substrate between the source and drain regions, and a gate insulating layer provided between the channel region and the gate electrode.
The first wiring comprises, for example, silicon, aluminum, tantalum, titanium, tungsten, molybdenum, an alloy thereof, tantalum nitride, titanium nitride, tungsten silicide, or molybdenum silicide.
It is natural capability of insulation is improved if an additional insulating film is formed by a method such as chemical vapor deposition(CVD), because above mentioned oxide has a good insulation. However, characteristic of the present invention is not to make the oxide insulating film in a homogeneous thickness around the material of the wiring over the whole surface, but to determine thicknesses of the oxide insulating film according to location thereof to accomplish the purpose.
The present invention is firstly related to an MIS (metal-insulator-semiconductor structure) transistor, and a manufacturing technology thereof with such wiring oxide as a mask. In the case of forming an impurity region(source, drain) of an MIS transistor by well known self-align method, a slight overlap was sometimes made between the gate electrode and the source region, drain region, because impurities were introduced with a gate electrode as a mask. In this case, an electric field was concentrated to a portion where the drain and the gate electrode were close to each other. That sometimes broke the gate insulating film near it.
This inventor found that by separating the gate electrode from at least one of the source and drain regions to provide an offset region between the gate electrode and at least one of the source and drain regions, such concentration of electric field could be prevented and the gate insulating film could be prevented from being broken. For example, the gate electrode is 500 to 5000 xc3x85 distant from at least one of the source and drain regions. Indeed, it was difficult to obtain such a minute offset region with good reproducibility by using a conventional method. In addition to the gate electrode, this inventor decided to use an oxide around the gate electrode as a mask when an impurity was introduced. Moreover, this inventor found that above mentioned purpose can be achieved by strictly controlling the thickness of this oxide to be the size of offset.
The inventor also found that characteristic of the MIS transistor changes according to the size of the offset made here. In general, if offset was big, dielectric strength of a transistor obtained was high, and leak current between the source and drain was small, but mobility was low. On the contrary, if offset was small, mobility was high, but dielectric strength was low.
For example, both a transistor with high dielectric strength and a transistor which can be driven fast were sometimes needed in the same substrate, but they were not made separately in such case. The present invention is firstly characterized in that such transistors with different characteristics are controlled by the size of offset(that is, thickness of oxide of wiring-gate electrode), and transistors appropriate for different purposes are formed in the same substrate.
For example, in a liquid crystal display of TFT active matrix type, a transistor with big offset is formed as TFTs for active matrix, and on the other hand, a transistor with small offset is formed as TFTs for peripheral circuits which must be driven fast, both of the transistors being formed on the same substrate. In addition, a structure comprising a logic circuit made of a transistor with small offset and an output transistor made of a transistor with big offset can be utilized for a peripheral circuit.
The present invention is secondly related to an MIS type transistor and a wiring connected to it. In a wiring in the same layer of the gate electrode of the MIS type transistor, oxide is made thick in the portion where this wiring is crossed with an upper wiring. On the other hand, an oxide film of the wiring of the gate electrode is thinned or is not formed at all. In this case, the transistor can be driven at a high speed because of small offset. On the other hand, at the portion where the wirings are crossed, an effect of good insulating property is obtained because of the thick oxide.
The present invention is thirdly related to a capacitor provided in a semiconductor circuit and to an integrated circuit with such a capacitor. They have a part of wirings as an electrode of a capacitor of which peripheral portion is covered with its oxide. On the other hand, in other portions of the wirings, peripheral portions of wirings are covered with an oxide at places where the wirings are crossed with upper wirings, too. By thinning oxide comprising a capacitor electrode, capacitance of the capacitor is made big. By thickening oxide at a place where wirings are crossed, and, by depositing additional oxide film on the place, insulating property between the wirings is improved and capacity coupling between them is decreased.
A semiconductor device in accordance with the present invention comprises:
a substrate;
a capacitor provided on said substrate;
a first wiring provided on said substrate in the same layer as a first electrode of said capacitor; and
a second wiring provided on said substrate in the same layer as a second electrode of said capacitor,
wherein said first wiring and said second wiring cross each other at a location B other than that of said capacitor, and said first wiring is provided with an oxide of a material of said first wiring on an upper or side surface of said first wiring, and said first electrode is provided with an oxide of a material of said first electrode on an upper surface of said first electrode at a thickness different from that of said oxide of the material of said first wiring at the location B.
The first wiring comprises, for example, silicon, aluminum, tantalum, titanium, tungsten, molybdenum, an alloy thereof, tantalum nitride, titanium nitride, tungsten silicide, or molybdenum silicide. The oxide of the material of the first wiring is thicker than the oxide of the material of the first electrode.
The present invention is fourthly related to a method of oxidizing wirings in forming such oxide. There are three methods. The first method is briefly shown in FIG. 19. As is shown in FIG. 19(A), a wiring 52 is formed directly or, if necessary, after deposition of a surface oxide film 51, on a substrate 50. A mask material 53 is provided to a portion forming a contact with upper wirings. It is important that the mask material has a function of blocking oxidizing effect, and is selected according to methods of oxidation. For example, in a method of thermal oxidation at a high temperature of several hundred centigrade, heat resistance is needed to a mask material. In this case, a material like silicon nitride which can be easily deposited and has good heat resistance and good resistance to oxidation is appropriate. If the wiring is oxidized at a lower temperature than above, more materials are useful. For example, if the process is performed at 400xc2x0 C. or less, an organic material such as polyimide can be utilized. Polyimide can be formed with a very low cost, because it does not need a vacuum apparatus for formation. Moreover, its mass productivity is good. Especially photosensitive polyimide(photoneece) is easy to use because patterning can be performed by a conventional photolithography method.
Oxidation of the wiring is performed in this condition with a first mask being provided selectively on the wiring, and a thin oxide film is formed around the wiring as is shown in FIG. 19(B). The wiring comprises, for example, silicon, aluminum, tantalum, titanium, tungsten, molybdenum, an alloy thereof, tantalum nitride, titanium nitride, tungsten silicide, or molybdenum silicide. A secondmask 55 is formed on a region containing at least a portion of the first mask, and oxidation of the wiring is performed in the same way. Thus a thick oxide 56 is formed as is shown in FIG. 19(C) In this way, an oxide with different thicknesses is obtained, which is characteristic of the present invention.
By removing the first mask and the second mask, a contact hole 57 is formed as is shown in FIG. 19(D). What is noteworthy is that the thickness of the oxide changes in steps until it reaches the contact hole. As a result, difference of the level to the contact hole can be decreased. FIGS. 19(E) and (F) show the case when an upper wiring 59 is connected to the contact hole 57. The upper wiring is formed on at least a portion of a region from which the first mask is removed by the step shown in FIG. 19(D). If etching selection ratio between an interlayer insulator 58 and wiring oxide 54, 56 is enough and the area of the contact formation region is wide enough, more gradual steps are obtainable as is shown in FIG. 19(E). The interlayer insulator 58 is not necessarily needed. Because the thickness of the oxide under the upper wiring 59 becomes smaller in steps in the direction of the contact hole, disconnection of the upper wiring is difficult to happen. This method is effective in the case that etching cannot be performed substantially, because etching of an oxide of wirings is difficult, or because enough selection ratio with another material cannot be obtained.
The second method is shown in FIG. 20. As is shown in FIG. 20(A), a wiring 62 is formed directly, or if necessary, after deposition of a surface oxide film 61, on a substrate 60. The wiring comprises, for example, silicon, aluminum, tantalum, titanium, tungsten, molybdenum, an alloy thereof, tantalum nitride, titanium nitride, tungsten silicide, or molybdenum silicide. A thin oxide 63 is formed by oxidizing the surface of it. As is shown in FIG. 20(B), a mask material 64 is formed in a portion forming a contact hole. Oxidation of the wiring 62 oxidized at a surface of the wiring is performed in this condition with a mask being provided selectively on the wiring, and though the portion covered with the mask material remains a thin oxide 66, but a thick oxide film 65 is formed on other portions. In this way, an oxide with different thicknesses which is characteristic of the present invention is obtained. Then, the mask is removed.
As is shown in FIG. 20(D), the region 66 covered with a thin oxide is etched, and a contact hole 67 is formed in said surface after the removal of the mask in at least a portion of a region from which the mask is removed by the removing step of FIG. 20(C). In this case, too, the thickness of the oxide changes in steps until it reaches the contact hole. As a result, difference of level to the contact hole can be decreased. FIGS. 20(E) and (F) show the case when an upper wiring 69 is connected to the contact hole 67. The upper wiring 69 is formed at least in a portion of the contact hole. An interlayer insulator 68 is not necessarily needed.
The third method is shown in FIG. 21. As is shown in FIG. 21(A), a wiring 72 is formed directly, or if necessary, after deposition of a substrate oxide film 71, on a substrate 70. The wiring comprises, for example, silicon, aluminum, tantalum, titanium, tungsten, molybdenum, an alloy thereof, tantalum nitride, titanium nitride, tungsten silicide, or molybdenum silicide. A thick oxide 73 is formed by oxidizing the surface of it. As is shown in FIG. 21(B), a thick oxide is etched by photolithography method, and a thin oxide 75 is provided. In this way, an oxide with different thicknesses which is characteristic of the present invention is obtained.
A contact hole 76 is formed further to a portion in which a thin oxide is formed, e.g. by selectively etching the wiring 72 oxidized at a surface of the wiring 72. In this case, too, the thickness of an oxide changes in steps until it reaches the contact hole, and different level to the contact hole can be decreased. An interlayer insulator is formed on the substrate after the etching for the formation of the contact hole 76. A contact hole is formed in the interlayer insulator. FIG. 21(D) and (E) show the case when an upper wiring 78 is connected to the contact hole 76. The upper wiring 78 is formed over the contact hole. The interlayer insulator 77 is not necessarily needed. In this method, when the thick oxide 73 is etched to make it a thin oxide 75, if an etching rate is not uniform, its thickness will not be homogeneous. Therefore, to make this method real, an etching technology of an oxide is important. On the other hand, in the first and second methods, the thickness of an oxide is decided by selective oxidation of wirings. For example, the thickness of an oxide is decided by temperature and time in the case of thermal oxidation, and it is decided by voltage applied in the case of anodic oxidation. As long as these parameters are fixed, the thickness of the oxide is equal. Therefore, these methods are more secure method and have higher reliability compared with the third method.